1. Field of the Invention
The invention relates to a semiconductor device and a method for manufacturing the same.
2. Background Art
Nonvolatile semiconductor memory devices of flash memory and the like conventionally are constructed by two-dimensionally integrating memory cells on a surface of a silicon substrate. Conversely, technology is proposed to three-dimensionally integrate memory cells for further improvement of the bit density. However, general three-dimensional devices suffer from increased costs accompanying increased lithography steps because several lithography steps are necessary for each layer of the device.
Conversely, collectively patterned three-dimensional stacked memory has been proposed (for example, refer to JP-A 2007-266143 (Kokai)). In such technology, for example, a stacked unit is formed on a silicon substrate by alternately stacking electrode films and insulating films. Through-holes are then made in the stacked unit by collective processing. A charge storage layer is formed on a side face of each through-hole, and silicon is filled into the interior of the through-hole to form a silicon pillar (columnar semiconductor). A charge storage layer-type memory cell is thereby formed at an intersection between each electrode film and the silicon pillar. Because the memory cells are formed collectively, the problems regarding cost are expected to be solved.
A semiconductor device having such a structure includes a first pillar provided in a first layer forming, for example, the memory cells to be directly linked to a second pillar provided in a second layer on the first layer forming, for example, a selection gate transistor portion.
At this time, lithography alignment shift occurs when forming the first pillar and the second pillar and is accompanied by difficulties during manufacturing. Therefore, technology is proposed to increase the diameter of the connection portion between the first pillar and the second pillar to increase the tolerance of the alignment shift (for example, refer to JP-A 2008-72051 (Kokai). However, the steps of such methods are complex, and room for improvement exists.
Further, deterioration of device characteristics of memory cells occurs when, for example, the through-hole forming the second pillar reaches the uppermost memory cell layer of the first layer when forming the second pillar.